1. Field of the Invention
The present invention relates to a voltage converter, and more particularly, to a voltage converter capable of avoiding a voltage drop occurring in an input signal.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram of a prior art converter 100. As shown in FIG. 1, the voltage converter 100 includes an inductor L, a feedback circuit 102, a voltage converting circuit 104, and a transistor Qp. The voltage converter 100 is used as a DC/DC converter for boosting a voltage level of an input voltage signal Vin and is coupled to an enable signal EN, wherein the enable signal EN is used to start the voltage converter 100. The voltage converting circuit 104 comprises an error amplifier OP1, a PWM (Pulse Width Modulation) control loop 106, and a transistor Qn. The PWM control loop 106 generates a plurality of voltage control signals Sn and Sp to control the conductance of the transistors Qn and Qp respectively. The voltage control signals Sn and Sp are complementary to each other, and their duty cycles are controlled by an output of the error amplifier OP1 (i.e. Verr). The inverting node of the error amplifier OP1 is used to receive a feedback voltage signal Vfb, and the non-inverting node of the error amplifier OP1 is utilized for receiving a reference voltage signal Vref, wherein the feedback voltage signal Vfb corresponds to an output voltage signal Vout, and the reference voltage signal Vref is a voltage signal whose voltage level increases with time after start-up and is provided by an external circuit (not shown in FIG. 1). For example, the reference voltage signal Vref is a linear signal in general. Additionally, the output voltage signal Vout is used as an input signal of the load 108. The output of the error amplifier OP1 (i.e. Verr) responds to the difference between the feedback voltage signal Vfb and the reference voltage signal Vref to control duty cycles of voltage control signals Sn and Sp that control on/off states of transistors Qn and Qp, and then a voltage level of the output voltage signal Vout will be stabilized. When the voltage level of the output voltage signal Vout is stabilized, the following equation is established:
                              V          out                =                              V            ref                    ×                                    (                                                R                  1                                +                                  R                  2                                            )                                      R              2                                                          Equation        ⁢                                  ⁢                  (          1          )                    
wherein R1 and R2 are resistors in the feedback circuit 102.
However, even though the voltage levels of voltage control signals Sn and Sp remain at a low voltage level and a high voltage level, respectively, a large amount of leakage current is still formed. This is because a body diode exists on the transistor Qp and is forward-biased to induce the leakage current. For example, a voltage level of the input voltage signal Vin is 3.3 volts and the body voltage of the body diode is 0.7V, and a voltage level of the output voltage signal Vout becomes 2.6V when the voltage levels of voltage control signals Sn and Sp remain at a low voltage level and a high voltage level respectively. Any integrated circuits, represented by the load 108 shown in FIG. 1 and coupled to the output voltage signal Vout, may be erroneously activated since the voltage level of the output voltage signal Vout, 2.6V is not equal to zero; furthermore, the non-zero voltage level of the output voltage signal Vout may provide the load 108 with a huge amount of static current leaked from the forward-biased body diode of the transistor Qp. For a mobile device using a single battery as its power supply, the above-mentioned condition would consume electric energy of the battery when the mobile device is not operating or idle.
Two prior art methods are provided for solving the above-mentioned problem. A first prior art method is to add a load switch between the transistor Qp and the load 108 to control if the electrical connection is established, where the load switch has a transistor with a body diode having a p-type region coupled to the load and an n-type region coupled to the preceding transistor Qp. The load switch is able to block the leakage current from being leaked through the forward-biased body diode of the transistor Qp to the load 108. However, in practice, the additional load switch increases both cost and area of the printed circuit board (PCB). Furthermore, the load switch lowers the energy transfer efficiency since the load switch itself actually consumes energy when conducting current due to inherent resistance.
In general, a second prior art method is often used to solve the leakage current problem caused by the forward-biased body diode. Please refer to FIG. 2 and FIG. 3. FIG. 2 is a diagram of another prior art converter 200. FIG. 3 is a timing diagram illustrating the operation of the prior art converter 200 shown in FIG. 2. As shown in FIG. 2, the voltage converter 200 includes an inductor L, a feedback circuit 202, a voltage converting circuit 204, a transmission switch 206, and a switch signal generator 208, wherein the voltage converting circuit 204 comprises an error amplifier OP1, a PWM control loop 210, and a transistor Qn. The operations and functions of the feedback circuit 202, the voltage converting circuit 204, and the PWM control loop 210 are the same as those of the above-mentioned feedback circuit 102, voltage converting circuit 104, and PWM control loop 106. Further description is therefore not included for brevity. The voltage converter 200 is coupled to an enable signal EN, which is used to start the voltage converter 200, and the output voltage signal Vout is used as an input signal of the load 212. The transmission switch 206 includes a transistor Qp, a first switch S1, and a second switch S2. The switch signal generator 208 respectively generates a first switch control signal C1 and a second switch control signal C2 to control the on/off statuses of the first switch S1 and second switch S2.
As shown in FIG. 3, before the voltage converter 200 is started, the first switch control signal C1 keeps a high logic level and a second switch control signal C2 keeps a low logic level, so the status of the first switch S1 is on (i.e. closed) and the status of the second switch S2 is off (i.e. open). Therefore, a PN junction is established between the body and the drain of the first transistor Qp where a p-type region is the drain and the n-type region is the body. No leakage current is allowed to be passed to the load 212 when the voltage control signals Sn and Sp are logic low and logic high respectively because the diode is reverse biased. When the voltage converter 200 is started by the enable signal EN at time T1 (i.e. a logic level of the enable signal EN is changed from a low logic level to a high logic level), the first switch control signal C1 changes from the high logic level to a low logic level and the second switch control signal C2 changes from the low logic level to a high logic level, so the status of the first switch S1 is changed to be off and the status of the second switch S2 is changed to be on. In this moment, a PN junction is established between the body and the source of the first transistor Qp where a p-type region is the source and the n-type region is the body. At the same time, the voltage level of the reference voltage signal Vref increases slowly from zero volts to a default value (e.g. 1.25 volts) according to the design of the feedback circuit 202. At this time, the voltage difference between voltage levels of the output of the voltage converting circuit 204 (i.e. Vin′) and of the output voltage signal Vout is large even though a body voltage Vd occurs at the body of the transistor Qp. The output capacitor Cout is then immediately charged with a large inrush current to make the voltage level of the output voltage signal Vout equal to the output of the voltage converting circuit 204 (i.e. Vin′) minus the body voltage Vd at time T2. After time T2, because the feedback voltage signal Vfb still follows the reference voltage signal Vref, the voltage level of the output voltage signal Vout increases slowly from the voltage level of the output of the voltage converting circuit 204 (i.e. Vin′) minus the body voltage Vd to a stable value (e.g. 5 volts) at time T3. Therefore, the transistor Qp conducts slowly during the period from time T2 to T3; however, a large inrush input current Iin during time T1 to T2 cannot be decreased. This will result in a voltage drop in the input voltage signal Vin (shown in FIG. 3). In a battery, if the situation of the voltage drop in the input voltage signal Vin is significant, other systems whose energy are provided by the battery may be activated at an inappropriate moment.